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Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond

on May 23, 2018 from 6:00 PM to 8:00 PM

Speaker Alvin Loke
Topic Info

This is an encore presentation of the Best Paper Award recipient at the 2018 Custom Integrated Circuits Conference (CICC).

The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.

Speaker Bio

Alvin is a Senior Directory of Technology at Qualcomm working on next-generation CMOS design/technology co-optimization and wireline for mobile ICs. Prior to Qualcomm, he worked on CMOS process integration at HP Labs and Chartered Semiconductor before shifting to wireline design at Agilent and AMD. He is an active volunteer in the IEEE Solid-State Circuits Society, having served as a CICC committee member, Chapter Chair, JSSC Guest Editor, and Distinguished Lecturer. He recently joined the VLSI Symposia committee and is the Solid-State Circuits Society Webinar Coordinator for North America. Alvin received his Bachelors from the University of British Columbia in engineering physics with highest honors, and Masters and PhD in electrical engineering from Stanford.

Location Qualcomm San Diego Campus (Sorrento Valley) Building AZ room A 10155 Pacific Heights Blvd. San Diego, CA 92121

Please see parking map attached.

6:00-6:30pm   Registration and Networking

6:30-8:00pm   Presentation and Q/A


Cost Free for IEEE members and Qualcomm employees $5 for non members

  File Date Uploaded
qualcomm AZ parking.jpg 05/09/18 09:48 AM

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